Embodiments of the present invention relate generally to a semiconductor memory apparatus and, more particularly, to a sensing enable signal control circuit configured to control a read operation of the semiconductor memory apparatus.
Generally, during a read operation, a semiconductor memory apparatus amplifies cell data through a bit line sense amplifier. Subsequently, an I/O sense amplifier receives the data from a bit line sense amplifier through local I/O lines LIO and LIOb, and then amplifies the data again. This amplified data is transferred to an output unit through global I/O lines GIO and GIOB.
The data is transferred from the I/O sense amplifier to the global I/O lines GIO and GIOB after a delay time that is determined by a sensing enable signal ‘IOSTB’, which is generated in response to a column select enable signal ‘YI’.
FIG. 1 is a circuit diagram shown for illustrating a read operation in an exemplary conventional semiconductor memory apparatus.
Referring to FIG. 1, a sensing enable signal generating unit 10 receives a column select enable signal ‘YI’ and a delay code to output a sensing enable signal ‘IOSTB’ by delaying the column select enable signal ‘YI’ by a delay time determined by the delay code.
An I/O sense amplifier 12 receives a first amplified data, which has been amplified by a bit line sense amplifier, through local I/O lines LIO and LIOb and then performs a secondary amplification (i.e., the I/O sense amplifier amplifies the first amplified data again) and latches the received data. As the sensing enable signal ‘IOSTB’ is enabled, a latched data is transferred to a pipe latch 16 via a multiplexer 14 through global I/O lines GIO and GIOB.
The data transferred to the pipe latch 16 is output to an output pad DQ through an output unit 18.
As mentioned above, in the exemplary conventional semiconductor memory apparatus, the time that the data stored in a memory cell is read out is varied according to the enable timing of the sensing enable signal ‘IOSTB’. The faster the generation time of the sensing enable signal ‘IOSTB’ is, the more a data access time tAA is reduced.
Therefore, a delay time is determined in such a manner that the sensing enable signal ‘IOSTB’ is enabled based on the sensing ability of the I/O sense amplifier 12.
That is, when a voltage difference between the local I/O lines LIO and LIOb exceeds a predetermined voltage (ΔV), the I/O sense amplifier 12 can obtain a sensing margin. However, it is necessary to take a time (tYIO) to obtain the sensing margin. Therefore, after the required time to obtain the sensing margin has expired, the sensing enable signal ‘IOSTB’ has to be enabled to carry out an exact read operation.
FIG. 2 is a timing chart showing an enable timing of the sensing enable signal based on the voltage difference between the local I/O lines LIO and LIOb in the exemplary conventional semiconductor memory apparatus.
Referring to FIG. 2, the column select enable signal ‘YI’ is enabled to a high level (the select enable signal is indicated by a solid line) and data is then loaded on a pair of the local I/O lines LIO and LIOb. After a period of time tYIO, the voltage difference between the local I/O lines LIO and LIOb is ΔV, the sensing enable signal ‘IOSTB’ is enabled (the sensing enable signal IOSTB is indicated by a dotted line) and the data stored in the cell is transferred to the global I/O lines GIO and GIOB.
At this time, the delay time (tYIO), which is the period of time between when the column select enable signal is enabled and when sensing enable signal ‘IOSTB’ is enabled, is determined by a simulation result of the semiconductor memory apparatus. However, in the actual semiconductor memory apparatus, the sensing enable signal ‘IOSTB’ is enabled after a delay time determined by the simulation and an additional margin ‘α’ (as a result, the total delay time=tYIO+α) in order to guarantee the reliability of the operation environment.
Furthermore, since the time required to obtain the sensing margin is varied according to external environments, such as pressure, voltage, and temperature (PVT), the duration of the enablement of the sensing enable signal ‘IOSTB’ enabled is determined according to a worst case scenario.
As mentioned above, the greater the delay of the enabling of the sensing enable signal ‘IOSTB’, the greater the delay in transferring the data to the global I/O lines GIO and GIOb, and the data access time tAA is also increased.
Accordingly there is a problem in the conventional semiconductor memory apparatus, in that the data access time tAA is unnecessarily increased, since the enable timing of the sensing enable signal ‘IOSTB’ is determined according to a deteriorated environment, even when a current external environment may be good.
To solve the above and other problems, an enable timing of the sensing enable time can be corrected by testing the read operation after mass producing the semiconductor memory apparatuses; however, testing every semiconductor memory apparatus and controlling the delay time accordingly, is very time consuming, and therefore very expensive.